The present invention generally relates to large scale integrated circuit (LSI) layout designing apparatuses, computer-implemented methods of designing LSI layout and computer readable storage mediums, and more particularly to a LSI layout designing apparatus and a computer-implemented method of designing LSI layout by computer aided design (CAD), and to a computer readable storage medium which stores a program for making a computer carry out a LSI layout design by such a LSI layout design method.
Recently, the number of elements in the LSIs has increased considerably, and the trend is for the functions of the LSIs to become more and more complex. In order to cope with the increasing elements and complexity of the LSIs, an electronic design automation (EDA) tool is essential when designing the LSIs.
Conventionally, the design process of the EDA is generally divided into a logic design process and a physical design process. A layout design process which designs the layout of the LSI is included in the physical design process.
A boundary between the logic design process and the physical design process originally is natural, and it is essentially unnecessary to integrate or feedback data between the logic design process and the physical design process, because the performance of the circuit is directly dependent upon a gate delay time. This gate delay time is the time required for a signal to propagate from an input terminal of the logic gate to an output terminal of the logic gate. In other words, the circuit performance is conventionally unaffected by a delay time generated in a wire which connects two logic gates.
For this reason, the person who designs the LSI designs the LSI using timing parameters which are based on characteristics of each of macro cells of the LSI. That is, the delay times of the connecting wires which are determined after determining the layout of the macro cells of the LSI have virtually no effect on the performance of the LSI. Accordingly, after making the logic design independently, the person who designs the LSI simply inputs the result of the logic design to an automatic LSI layout designing apparatus. The result of the logic design is often called a net list or logic circuit data.
However, the semiconductor production technology has developed considerably in recent years. As a result, the size of various elements have become extremely small, transistors having extremely high-speed switching capability have been developed, and the gate delay time has become extremely short. Consequently, the gate delay time is no longer the primary factor which determines the performance of the LSI, and instead, the delay times of the connecting wires have become dominant among the signal delay times. Hence, it is becoming more and more difficult to satisfy the timing specifications of the LSI when designing the LSI.